Bài giảng Vi xử lý - Chương 3: Họ vi điều khiển 8051

CHƯƠNG 3
HỌ VI ĐiỀU KHIỂN 8051
Hiệu đính từ slide của thầy Hồ Trung Mỹ
Bộ môn Điện tử - DH BK TPHCM
1
Nội dung
3.1 Giới thiệu họ vi điều khiển 8051 
3.2 Kiến trúc phần cứng 8051
3.3 Các phương pháp định địa chỉ
2
3.1 Giới thiệu 
họ vi điều khiển 8051
3
Các kiến trúc vi điều khiển
CPU
Program 
+ Data
Address Bus
Data Bus
Memory
Von Neumann
Architecture
0
2n
CPU
Program
Address Bus
Data Bus
Harvard
Architecture
Memory
Data
Address Bus
Fetch Bus
0
0
4
Họ VĐK 8051
• 8051 là vi điều khiển đầu tiên của họ vi điều khiển
MCS51 được Intel sản xuất vào năm 1980. Họ MCS51
là họ 8-bit có khả năng định địa chỉ 64KB bộ nhớ
chương trình và 64KB bộ nhớ dữ liệu.
5
Comparison of MCS-51 ICs
2128 bytes0K8031
2128 bytes4K ROM8051
TimersOn-Chip Data 
Memory
On-Chip Code 
Memory
Part 
Number
3256 bytes8K EPROM8752
3256 bytes0K8032
3256 bytes8K ROM8052
2128 bytes4K EPROM8751
6
3.2 Kiến trúc phần cứng 8051
7
Sơ đồ khối 8051/8031
8
9
Ý nghĩa các chân trên MCU 8051
• Port 0 (Cổng 0)
Port 0 là một port hai chức năng trên các chân 32–39. Trong các thiết kế cỡ nhỏ 
(không dùng bộ nhớ mở rộng) nó có chức năng như các đường I/O. Đối với các 
thiết kế lớn với bộ nhớ mở rộng, nó được dồn kênh giữa bus địa chỉ và bus dữ 
liệu.
• Port 1 (Cổng 1)
Port 1 là cổng dành riêng cho nhập/xuất trên các chân 1–8. Các chân được ký 
hiệu P1.0, P1.1, P1.2, ... có thể dùng cho giao tiếp với các thiết bị ngoài nếu 
cần. Port 1 không có chức năng khác, vì vậy chúng chỉ được dùng cho giao tiếp 
với các thiết bị ngoài. 
• Port 2 (Cổng 2)
Port 2 là một cổng công dụng kép trên các chân 21–28 được dùng như các 
đường xuất nhập hoặc là byte cao của bus địa chỉ đối với các thiết kế dùng bộ 
nhớ mở rộng.
• Port 3 (Cổng 3)
Port 3 cũng là một cổng công dụng kép trên các chân 10–17. Các chân của port 
này có nhiều chức năng, các công dụng chuyển đổi có liên hệ với các đặc tính 
đặc biệt của 8051/8031 10
Các chức năng chuyển đổi ở Port 3
11
12
Cấu trúc cổng I/O
• Khả năng lái là 4 tải TTL loại LS (Low Power 
Schottky) với các cổng P1, P2, và P3; và 8 tải 
TTL loại LS với cổng P0. 
• Chú ý là điện trở kéo lên bên trong không có 
trong Port 0 (ngoại trừ lúc làm việc như bus dữ 
liệu / địa chỉ bên ngoài). Điện trở kéo lên có 
thể được sử dụng với P0 tùy theo đặc tính vào 
của thiết bị mà nó lái.
13
14
15
A Pin of Port 1 
D Q
Vcc
Load(L1)
Read latch
Internal CPU P1.X 
TB2
8051 IC
Clk Q
Read pin
Write to latch
bus
M1
pinP1.X 
TB1
⌦P0.x
16
Writing “1” to Output Pin P1.X
D Q
Vcc
Load(L1)
Read latch
Internal CPU P1.X 
2. output pin is
Vcc1. write a 1 to the pin
1
TB2
Clk Q
Read pin
Write to latch
bus
M1
pinP1.X 
8051 IC
0 output 1
TB1
17
Writing “0” to Output Pin P1.X
D Q
Vcc
Load(L1)
Read latch
Internal CPU P1.X 
2. output pin is 
ground1. write a 0 to the pin
0
TB2
Clk Q
Read pin
Write to latch
bus
M1
pinP1.X 
8051 IC
1 output 0
TB1
18
Reading “High” at Input Pin
D Q
Vcc
Load(L1)
Read latch
Internal CPU bus P1.X pin
2. MOV A,P1 
external pin=High
1. write a 1 to the pin MOV 
P1,#0FFH
1 1
TB2
Clk Q
Read pin
Write to latch M1
P1.X 
8051 IC
0
3. Read pin=1 Read latch=0 
Write to latch=1
TB1
19
Reading “Low” at Input Pin
D Q
Vcc
Load(L1)
Read latch
Internal CPU bus P1.X pin
2. MOV A,P1
external pin=Low1. write a 1 to the pin
MOV P1,#0FFH
1 0
TB2
Clk Q
Read pin
Write to latch M1
P1.X 
8051 IC
0
3. Read pin=1 Read latch=0 
Write to latch=1
TB1
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Other Pins
• P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not 
connects to Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X. 
• However, for a programmer, it is the same to program 
P0, P1, P2 and P3.
• All the ports upon RESET are configured as output.
21
A Pin of Port 0 
D Q
Read latch
Internal CPU P0.X 
TB2
8051 IC
Clk Q
Read pin
Write to latch
bus
M1
pinP1.X 
TB1
⌦P1.x
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Port 0 with Pull-Up Resistors
P0.0
P0.1DS5000
Vcc
10 K
P
o
rt 
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
8751
8951
P
o
rt 
0
23
Port 3 Alternate Functions
12INT0P3.2
11TxDP3.1
10RxDP3.0
PinFunctionP3 Bit
17RDP3.7
16WRP3.6
15T1P3.5
14T0P3.4
13INT1P3.3
⌦
24
Chu kỳ lệnh, chu kỳ máy và trạng thái
25
12MHz internal clock
6 machine cycles
26
Dồn kênh bus địa chỉ (byte thấp) và bus dữ liệu
27
Truy cập bộ nhớ chương trình bên ngoài
28
29
30
31
Cấu trúc bộ nhớ 8051
32
Tóm tắt bộ nhớ dữ liệu trên chip
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Bộ nhớ dữ liệu 8051
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Lower 128 Bytes of Internal RAM
20H-2FH: 128 Bit-addressable bits occupying bit address 00H-7FH.
30H-7FH: General purpose RAM (can be accessed through direct or 
indirect addressing)
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Upper 128 Bytes of Internal RAM
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Vùng nhớ 8032/8052
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MOV A, 5FH
MOV A, FFH
MOV Ri, #5FH ( I = 0 or 1)
MOV A, @Ri
Tóm tắt thanh ghi PSW
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Tóm tắt thanh ghi PCON
39
Truy cập bộ nhớ chương trình bên ngoài
40
Định thì đọc bộ nhớ chương trình bên ngoài 
(PCH byte của PC và PCL là byte thấp của PC)
41/PSEN ở mức thấp trong thời gian lấy lệnh
Truy cập bộ nhớ dữ liệu bên ngoài
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Giản đồ định thì cho lệnh MOVX
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Mạch giải mã địa chỉ các EPROM 8KB và RAM 8KB với hệ 8051
44
Phủ lấp vùng nhớ dữ liệu và 
chương trình bên ngoài
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Hoạt động reset
46
Mạch reset hệ thống
47
Các giá trị thanh ghi sau khi reset hệ thống
48
3.3 CÁC PHƯƠNG PHÁP 
ĐỊNH ĐỊA CHỈ
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Các cách định vị địa chỉ 
• Be the way to access data
• 8051 has different addressing mode:
– Immediate (constant data)
– Register (register data)
– Direct (RAM data)
– Register indirect (RAM data)
– Indexed (ROM data)
– relative addressing
– Absolute addressing
– Long addressing
50
8051 
Instruction 
Format
51
Addressing Modes 
1) Immediate Mode – specify data by its value
mov A, #0 ;put 0 in the accumulator
;A = 00000000
mov R4, #11h ;put 11hex in the R4 register
;R4 = 00010001
mov B, #11 ;put 11 decimal in b register
;B = 00001011
mov DPTR,#7521h ;put 7521 hex in DPTR
;DPTR = 0111010100100001
52
Addressing Modes 
1) Immediate Mode – continue
MOV DPTR,#7521h 
MOV DPL,#21H
MOV DPH, #75
COUNT EQU 30
~
~
mov R4, #COUNT 
MOV DPTR,#MYDATA
~
~
0RG 200H
MYDATA:DB “HELLO”
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Add “#” before any immediate data
Only the source operand can be immediate
Add “h” after a base-16 number, “b” after a 
base-2 number; otherwise assumed base-10
Use ‘ ’ to enclose any character
Notes of Immediate Addressing
Precede all base-16 numbers that begin with 
A-F by a “0”
MOV A,#ABh
MOV A,#0ABH
54
8051 Instruction Format
Op code Immediate 
data
• immediate addressing 
add a,#3dh ;machine code=243d
Op code Direct address
• Direct addressing
mov r3,0E8h ;machine code=ABE8
55
Addressing Modes
2) Direct Mode – play with R0-R7 by direct 
address
MOV A,4 ≡ MOV A,R4
MOV A,7 ≡ MOV A,R7
MOV 7,6 ≡ MOV R7,R6
MOV R2,#5 ;Put 5 in R2
MOV R2,5 ;Put content of RAM at 5 in R2
56
Addressing Modes
2) Direct Mode – specify data by its 8-bit address
Usually for 30h-7Fh of RAM
Mov a, 70h ; copy contents of RAM at 70h to a
Mov R0,40h ; copy contents of RAM at 40h to a
Mov 56h,a ; put contents of a at 56h
Mov 0D0h,a ; put contents of a into PSW
57
Examples of Direct Addressing
Instruction Operation
MOV 80h, A or
MOV P0, A
Copy contents of register A to location 80h 
(Port 0 latch)
MOV A, 80h or
MOV A, P0
Copy contents of location 80h (Port 0 pins) to 
register A
Note: No “#” sign in the instruction
MOV A, ABC Copy contents from direct address with label 
ABC to register A
MOV R0, 12h Copy contents from RAM location 12h to 
register R0
MOV 0A8h, 77h or
MOV IE, 77h
Copy contents from RAM location 77h to IE 
register of SFRs MOV direct,direct
ABC EQU 80h ; equate
MOV A, ABC ; Port 0 to A
58
Examples of Direct Addressing
MOV A, 2 ; copy location 02 (R2) to A
MOV B, 2 ; copy location 02 (R2) to B
MOV 7, 2 ; copy location 02 to 07 (R2 to R7)
; since “MOV R7, R2” is invalid
MOV DIRECT, DIRECT
59
Stack and Direct Addressing Mode
Only direct addressing mode is allowed for 
pushing onto the stack
PUSH A (Invalid)
PUSH 0E0h (Valid)
PUSH direct
POP direct
PUSH R3 (Invalid)
PUSH 03 (Valid)
POP R4 (Invalid)
POP 04 (Valid)
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Example
PUSH 05 ; push R5 onto stack
PUSH 06 ; push R6 onto stack
PUSH 0E0h ; push register A onto stack
Show the code to push R5, R6, and A onto the stack and then pop 
them back into R2, R3, and B, where register B = register A, R2 = R6, 
and R3 = R5.
POP 0F0h ; pop top of stack into register B
; now register B = register A
POP 02 ; pop top of stack into R2
; now R2 = R6
POP 03 ; pop top of stack into R3
; now R3 = R5
61
The address value is limited to one byte, 00 – FFh (128-
byte RAM and SFR)
Using MOV to move data from itself to itself can lead to 
unpredictable results error
MOV data to a port changes the port latch
MOV data from port gets data from port pins
Notes of Direct Addressing
Eg. MOV A, A
62
Addressing Modes
3) Register Addressing – either source or 
destination is one of CPU register
MOV R0,A
MOV A,R7
ADD A,R4
ADD A,R7
MOV DPTR,#25F5H
MOV R5,DPL
MOV R1,DPH
Note that MOV R4,R7 is incorrect 63
8051 Instruction Format
Op code n n n
• Register addressing
070D E8 mov a,r0 ;E8 = 1110 1000
070E E9 mov a,r1 ;E9 = 1110 1001
070F EA mov a,r2 ;EA = 1110 1010
0710 ED mov a,r5 ;ED = 1110 1101
0711 EF mov a,r7 ;Ef = 1110 1111
0712 2F add a,r7
0713 F8 mov r0,a
0714 F9 mov r1,a
0715 FA mov r2,a
0716 FD mov r5,a
0717 FD mov r5,a 
64
The most efficient addressing mode:
No need to do memory access 
Instructions are much shorter 
Result: speed (hence efficiency) increased
We can move data between Acc and Rn (n = 0 
Notes of Register Addressing
to 7) but movement of data between Rn
registers is not allowed
e.g. MOV R4, R7 (Invalid)
;Use the following :
MOV A, R7
MOV R4,A
MOV R4,07H ; this is direct addressing mode
65
Review Questions
1. Can the programmer of a microcontroller make up 
new addressing modes?
2. Show the instruction to load 1000 0000 (binary) into 
R3.
3. Why is the following invalid? “MOV R2, DPTR”
4. True or false. DPTR is a 16-bit register that is also 
accessible in low-byte and high-byte formats.
5. Is the PC (program counter) also available in low-
byte and high-byte formats?
66
Addressing Modes
4) Register Indirect – the address of the source or 
destination is specified in registers
Uses registers R0 or R1 for 8-bit address:
mov psw, #0 ; use register bank 0
mov r0, #3Ch
mov @r0, #3 ; M[3Ch]  3
Uses DPTR register for 16-bit addresses:
mov dptr, #9000h ; dptr  9000h
movx a, @dptr ; a  M[9000h]
Note that 9000h is an address in external memory
67
8051 Instruction Format
Op code i
• Register indirect addressing
mov a, @Ri ; i = 0 or 1
070D E7 mov a,@r1
070D 93 movc a,@a+dptr
070E 83 movc a,@a+pc
070F E0 movx a,@dptr
0710 F0 movx @dptr,a
0711 F2 movx @r0,a
0712 E3 movx a,@r1 68
Use Register Indirect to access upper 
RAM block (+8052)
69
Use a register to hold the address of the operand; i.e. using 
a register as a pointer
Only R0 and R1 can be used when data is inside the CPU 
(address ranges from 00h – 7Fh) eg. MOV A, @R1
R0 ,R1 and DPTR can be used when addressing external 
memory locations eg. MOVX A,@R1 MOVX A,@DPTR
Must put a “@” sign before the register name
Register Indirect Addressing
70
Program 
memory
Addresses
ACC
R0ADD A, @R0200
201
10
31
ACC
R0
31
22⊕
Register Indirect Addressing (eg. ADD A,@R0)
AfterBefore
Data 
memory
1231
32
30
8051 Internal data memory
71
Instruction Operation 
MOV @R1, A Copy the data in A to the address pointed to by 
the contents of R1 
MOV A, @R0 Copy the contents of the address pointed to by 
register R0 to the A register 
MOV @R1, #35h Copy the number 35h to the address pointed to 
Examples of Indirect Addressing
by register R1 
MOV @R0, 80h or 
MOV @R0, P0 
Copy the contents of the port 0 pins to the 
address pointed to by register R0. 
MOVX A, @R0 Copy the contents of the external data address 
pointed to by register R0 to the A register 
MOVX A, @DPTR Copy the contents of the external data address 
pointed to by register DPTR to the A register 
MOV @Ri,#data where i = 0 or 1
72
Write a program segment to copy the 
value 55h into RAM memory locations 
40h to 44h using:
(a) Direct addressing mode;
Example
(b) register indirect addressing mode 
without a loop; and
(c) with a loop
73
MOV A, #55h ; load A with value 55h
MOV 40h, A ; copy A to RAM location 40h
MOV 41h, A ; copy A to RAM location 41h
Solution to Example (a)
Direct addressing mode
MOV 42h, A ; copy A to RAM location 42h
MOV 43h, A ; copy A to RAM location 43h
MOV 44h, A ; copy A to RAM location 44h
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MOV A, #55h ; load A with value 55h
MOV R0, #40h ; load the pointer. R0 = 40h
MOV @R0, A ; copy A to RAM location R0 points to
INC R0 ; increment pointer. Now R0 = 41h
MOV @R0, A ; copy A to RAM location R0 points to
Solution to Example (b)
register indirect addressing mode without a loop
INC R0 ; increment pointer. Now R0 = 42h
MOV @R0, A ; copy A to RAM location R0 points to
INC R0 ; increment pointer. Now R0 = 43h 
MOV @R0, A ; copy A to RAM location R0 points to
INC R0 ; increment pointer. Now R0 = 44h
MOV @R0, A ; copy A to RAM location R0 points to
75
MOV A, #55h ; A = 55h
MOV R0, #40h ; load pointer. R0 = 40h, RAM add.
MOV R2, #05 ; load counter, R2 = 5
AGAIN: 
MOV @R0, A ; copy 55A to RAM location R0 points to
INC R0 ; increment R0 pointer
Solution to Example (c) Loop method
DJNZ R2, AGAIN ; loop until counter = zero 
“DJNZ” : decrement and jump if Not Zero
DJNZ direct, relative
DJNZ Rn, relative where n = 0,1,,,7
MOV R2, #05h ; example
LP: 
;--------------------------------
; do 5 times inside the loop
;--------------------------------
DJNZ R2, LP ; R2 as counter
76
Example (looping)
Write a program segment to clear 15 RAM 
locations starting at RAM address 60h.
CLR A ; A = 0
MOV R1, #60h ; load pointer. R1 = 60h
MOV R7, #15 ; load counter, R7 = 15 (0F in HEX)
AGAIN: MOV @R1, A ; clear RAM location R1 points to
INC R1 ; increment R1 pointer
DJNZ R7, AGAIN ; loop until counter = zero 
; clear one ram location at address 60h
CLR A
MOV R1,#60h
MOV @R1,A
Setup a loop using DJNZ and register R7 as counter
77
Example (block transfer)
Write a program segment to copy a block of 10 bytes of 
data from RAM locations starting at 35h to RAM 
locations starting at 60h.
MOV R0, #35h ; source pointer
MOV R1, #60h ; destination pointer
MOV R3, #10 ; counter
BACK:
MOV A, @R0 ; get a byte from source
MOV @R1, A ; copy it to destination
INC R0 ; increment source pointer
INC R1 ; increment destination pointer
DJNZ R3, BACK ; keep doing it for all ten bytes
78
Using pointer in the program enables handling 
dynamic data structures an advantage
Dynamic data: the data value is not fixed
In this mode, we can defer the calculation of the 
address of data and the determination of the amount 
of memory to allocate at (program) runtime (eg. 
Notes of Indirect Addressing
MOV A, @R0)
Register or direct addressing (eg. MOV A, 30H) cannot be used ,
since they require operand addresses to be known at assemble-time.
79
Addressing Modes
5) Register Indexed Mode – source or 
destination address is the sum of the base 
address and the accumulator (Index)
• Base address can be DPTR or PC
mov dptr, #4000h
mov a, #5
movc a, @a + dptr ;a  M[4005]
80
Addressing Modes
5) Register Indexed Mode continue
• Base address can be DPTR or PC
ORG 1000h
1000 mov a, #5
1002 movc a, @a + PC ;a  M[1008]
1003 Nop
• Lookup Table 
• MOVC only can read internal code memory
PC
81
Using a base register (starting point) and an 
offset (how much to parse through) to form 
the effective address for a JMP or MOVC
instruction
Indexed Addressing
MOVC A, @A+DPTR
MOVC A, @A+PC
JMP @A+DPTR
Used to parse through an array of items or a 
look-up table
Usually, the DPTR is the base register and the 
“A” is the offset
A increases/decreases to parse through the 
list
82
Program 
memory
ACC
DPTR
00 10
ACC
56⊕
Indexed Addressing Example: MOVC A,@A+DPTR
AfterBefore
MOVC A, @A + DPTR2000
2001
41 3156
83
Instruction Operation 
MOVC A, @A + DPTR Copy the code byte, found at the ROM 
address formed by adding register A and the 
DPTR register, to A 
MOVC A, @A + PC Copy the code byte, found at the ROM 
Examples of Indexed Addressing
address formed by adding A and the PC, to A 
JMP @A + DPTR Jump to the address formed by adding A to 
the DPTR, this is an unconditional jump and 
will always be done. 
84
Example (look-up table)
Write a program to get the x value from P1 and 
send x2 to P2, continuously.
ORG 0
MOV DPTR, #300h ; load look-up table address
MOV A, #0FFh ; A = FF
MOV P1, A ; configure P1 as input port
BACK: MOV A, P1 ; get X
MOV A, @A+DPTR ; get X square from table
MOV P2, A ; issue it to P2
SJMP BACK ; keep doing it
ORG 300h
TABLE:DB 0, 1, 4, 9, 16, 25, 36, 49, 64, 81
END 
85
Review Questions
1. The instruction “MOV A, 40h” uses ________ 
addressing mode. Why?
2. What address is assigned to register R2 of bank 0?
3. What address is assigned to register R2 of bank 2?
4. What address is assigned to register A?
5. Which registers are allowed to be used for register 
indirect addressing mode if the data is in on-chip 
RAM?
86
Access to Accumulator
• A register can be accessed by direct and register
mode
• This 3 instruction has same function with different
code
0703 E500 mov a,00h
0705 8500E0 mov acc,00h
0708 8500E0 mov 0e0h,00h
• Also this 3 instruction 
070B E9 mov a,r1
070C 89E0 mov acc,r1
070E 89E0 mov 0e0h,r1 87
Access to SFRs
• B – always direct mode - except in MUL & DIV
0703 8500F0 mov b,00h
0706 8500F0 mov 0f0h,00h
0709 8CF0 mov b,r4
070B 8CF0 mov 0f0h,r4
• P0~P3 – are direct address 
0704 F580 mov p0,a
0706 F580 mov 80h,a 
0708 859080 mov p0,p1
• Also other SFRs (pcon, tmod, psw,.)
88
SFRs Address
All SFRs such as
(ACC, B, PCON, TMOD, PSW, P0~P3, ) 
are accessible by name and direct 
address
But
both of them 
Must be coded as direct address
89
8051 Instruction Format
• 6) relative addressing
here: sjmp here ;machine code=80FE(FE=-2)
Range = (-128 ~ 127)
• 7) Absolute addressing (limited in 2k current mem block)
Op code Relative address
A10-
A8 Op code
0700 1 org 0700h
0700 E106 2 ajmp next ;next=706h
0702 00 3 nop
0703 00 4 nop
0704 00 5 nop
0705 00 6 nop
7 next:
8 end
A7-A0 07FEh
90
Tính toán offset với định địa chỉ tương đối
91
Used in jump (“JMP”) instructions
Relative address: an 8-bit value (-128 to 
+127)
Relative Addressing SJMP relative
DJNZ direct, relative
DJNZ Rn, relative, where n=0,1,,,7
You may treat relative address as an 
offset
Labels indicate the JMP destinations (i.e. 
where to stop)
Assembler finds out the relative address 
using the label
92
The relative address is added to the PC
The sum is the address of the next 
instruction to be executed
Relative Addressing
As a result, program skips to the desired 
line right away instead of going through 
each line one by one
Labels indicate the JMP destinations (i.e. 
where to stop).
93
Branch Opcode
Offset
Next Opcode
Program Counter
Relative Addressing
Program counter + offset 
= Effective address 
= address of next instruction
+ Offset
Next Instruction
94
Instruction Operation 
SJMP NXT Jump to relative address with the label 'NXT'; this 
is an unconditional jump and is always taken. 
DJNZ R1, DWN Decrement register R1 by 1 and jump to the 
relative address specified by the label 'DWN' if 
Examples of Relative Addressing
the result of R1 is not zero. 
0035
95
Only used with the instructions ACALL and 
AJMP
Similar to indexed addressing mode
The largest “jump” that can be made is 2K
Absolute Addressing ACALL address11
AJMP address11
211 = 2048=2K
The subroutine called must therefore start within the 
same 2K Block of the program memory as the first 
byte of the instruction following ACALL.
96
Absolute Addressing
ACALL address11
AJMP address11ORG 00H ; reset location
LJMP START ; 3 bytes instruction
ORG 3FFEH
START: ACALL FORWARD ; 2 bytes instruction
; now code address at 4000H
LJMP TEST
ORG 47FFH ; 010001111111111B
FORWARD: 
RET
ORG 5800H ; 0101100000000000B
BACKWARD:
RET
ORG 5FFDH
TEST: ACALL BACKWARD ; 2 bytes instruction
; now code address at 5FFFH
SJMP $
END
97
8051 Instruction Format
• Long distance address
• Range = (0000h ~ FFFFh)
0700 1 org 0700h
Op code A15-A8 A7-A0
0700 020707 2 ajmp next ;next=0707h
0703 00 3 nop
0704 00 4 nop
0705 00 5 nop
0706 00 6 nop
7 next:
8 end
98
Bài tập 1
Cho biết mã máy và các cách định địa chỉ 
của các lệnh sau:
1. MOVX @DPTR, A
2. SETB P3.1
3. ADD A, R3
4. MOV A, #0FBH
5. MOV A, @R1
6. MOV 41H, A
99
Bài tập 2
1. Viết các lệnh thực hiện cất giá trị FFH 
vào RAM dữ liệu bên ngoài ở địa chỉ 
19A3H.
2. Sau đoạn chương trình này, cho biết các 
địa chỉ bit có nội dung là 1:
a) MOV 25h, #13h 
b) MOV R0, #22h 
c) MOV @R0, 25h
100
Bài tập 3
1. Cho biết mã máy sau biểu diễn lệnh/tác vụ gì?
75H, 8AH, E7H
2. Giả sử lệnh
AJMP LABEL
trong bộ nhớ mã ở địa chỉ 1600H và 1601H, 
và nhãn LABEL ứng với lệnh ở địa chỉ 1723H
a) Cho biết mã máy của lệnh này?
b) Lệnh này có hợp lệ không khi LABEL ứng với lệnh 
ở địa chỉ 1A23H? Giải thích 
101